In communication and network chips, for a communication process in which there are multiple groups of signals between multiple modules of different clock domains, to ensure correctness of data reading and writing, it is required to ensure that a precedence relationship between read and write requests keeps consistent with the time order. Therefore, order-preserving processing is required.
For example, in a complicated application scenario, in a first clock cycle, a device A requests a read operation on an address 0; in a second clock cycle, a device B requests a write operation on the address 0; in a third clock cycle, a device C requests the read operation on the address 0; in a fourth clock cycle, a device D requests the read operation on the address 0; in a fifth clock cycle, a device E requests the write operation on the address 0; in the sixth clock cycle, a device F requests the read operation on the address 0, and so on. To ensure correctness of data reading and writing, the controller needs to perform the read and write operations on the memory according to the foregoing order exactly. Otherwise, disorder will occur, which results in system errors.
Currently, in an existing signal order-preserving method, a manner of write confirmation is generally adopted for order-preserving. For an address, the controller is not allowed to perform the read operation on the address until a write confirmation signal of the address is returned. Through such a signal order-preserving method, delay caused by the write confirmation deepens buffering of a subsequent request source, and thereby intensifies the coupling extent between modules or devices on which there is an order-preserving requirement. Moreover, the delay caused by the write confirmation makes subsequent requests intermittent. Consequently, the system performance is not steady, so it is difficult to meet demands for high quality.